1 results found for Jerry Kaczynski , displaying items 1 - 1
September 2004[News Feature] Facing Up To Today’s FPGA Verification Challenges
Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with environments using Domain Specific Languages, such as Matlab. To speed up testbench simulations, patches written in C/C++ are frequently used. Sometimes, when simulation is still too slow hardware acceleration may be necessary. In the last two years embedded systems found their way...
