Traditionally, digital logic has not consumed significant static power, but this has changed dramatically as process nodes shrink. Leakage current in digital logic is now the primary challenge for FPGAs as process geometries decrease. If power-reduction strategies are not employed, power consumption becomes a critical issue as static power can increase dramatically at the 65-nm process node. Static power consumption rises largely because of increases in various

sources of leakage current (Fig. 1). Power consumption is composed of static and dynamic power. Static power is the power consumed by an FPGA when it’s programmed with a programmer object file (.pof), but no clocks are operating. Both digital and analog logic consume static power. In an analog system, static power primarily consists of the quiescent current of the analog circuit based on its interface (Fig. 2).

Dynamic power is the added power consumed when the device is operating, which is caused by toggling signals and charging and discharging capacitive loads. The main variables that affect dynamic power are capacitance charging and the supply voltage, as well as the clock frequency (Fig. 3).

Dynamic power decreases with Moore’s Law by taking advantage of process node shrinks to reduce capacitance and voltage. The challenge is when more circuits are implemented with each process shrink and the maximum clock frequency increases.

While the power reduction declines for an equivalent circuit from process node to process node, the FPGA capacity keeps doubling. On top of that, the maximum clock frequency keeps increasing.

FPGA ARCHITECTURE

Advances in architecture, process technology, and circuit techniques help attack these different power challenges. One such example is Altera’s Stratix III FPGA.

The company’s Programmable Power Technology helps reduce power in high-end FPGAs. Traditionally, all high-performance FPGAs are implemented with a highperformance fabric, where every logic element (LE) provides the maximum performance with a subsequent high leakage power.

Programmable Power Technology takes advantage of the fact that most circuits in a design have excess slack and therefore don’t require the highest performance logic. Figure 4 shows a typical excess slack histogram, where the majority of the paths (on the left) have slack and only a few critical paths (on the right) need the highest performance logic to meet timing requirements.

With Programmable Power Technology, the logic fabric of Stratix III can be programmed at the logicarray- block (LAB) level by providing high-speed or low-power logic, depending on what the specific logic path requires (Fig. 5). In this way, the small percentage of timing-critical circuits is “selected” to the high-speed setting, with the remainder using the low-power setting, resulting in a 70% drop in leakage power for the lowpower logic. Placing unused logic, as well as DSP blocks and TriMatrix memory into the low-power modes, further decreases power.

SELECTABLE CORE VOLTAGE

Selectable core voltage lets designers use a 0.9- or 1.1-V core voltage based on performance requirements. The 0.9-V core voltage provides the overall minimum dynamic and leakage power, while the 1.1-V core voltage delivers the overall highest performance. Dynamic power scales with the square of core voltage, while static power scales by the power of 2.5 of core voltage.

The selectable core voltage input can be set to 0.9 V or 1.1 V during board design. This core voltage supplies all LABs, memories, and DSP functions in the core fabric. The selectable core voltage affects the fabric performance, so when a device and speed grade are selected in the software, a core voltage selection is also required. The software uses timing and power models specific to the selected core voltage to implement all timing-dependent and power-dependent analysis and optimization.

When choosing which core voltage to use, a designer must consider the system performance requirements reported from the timing analysis. If a system’s performance requirements can be met with 0.9 V, they always produce lower power than when using 1.1 V.

MERGING TECHNOLOGIES

Combining Programmable Power Technology and selectable core voltage delivers various performance and power operating points that achieve over 50% power reduction at 1.1 V (Fig. 6). Static power varies considerably depending on the use of the various resources, such as DSP blocks and TriMatrix memory blocks.

The combined static and dynamic power varies across combinations of core voltage and percentage of highspeed versus low-power logic. In most designs, where maximum FPGA performance isn’t required, the total power of a design can be reduced by as much as 50% or more.

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