According to market researcher DisplaySearch, approximately 22 million LCDs will be used in by 2008 (the total was near 12 million in 2004). The interfaces between the graphic controller as a video source and the timing controller, which distribute this information to the individual pixels of the LCD display, will constitute a very important system function (Fig. 1). The frequencies, as well as the data and clock rates, occurring with the transmission paths of remote, increasingly larger and higher-resolution LCD modules can’t be controlled as analogue video signals. Nor can they be covered by conventional digital automotive communication standards (CAN, MOST, or most recently by FlexRay). USB and "Firewire" IEEE1394, in their electronic and optical versions, are mainly used for in-car driver information and entertainment systems. Because of the enormous protocol layer overhead, however, they don’t represent a cost-efficient system solution for a pure, transparent function for video raw data transfer to a display.
Since the end of the 90s, the differentiated signalling standard LVDS (low-voltage differential signalling) has established itself in its serialiser/deserialiser (SerDes) version in this field. Multiple serialiser-deserialiser designs have been developed to further refine this approach for specific requirements in the automotive sector. Minimising the pair of wires in transmission cables is an important development trend in this case. That’s because significant system costs aren’t included in the actual transmission components, but rather in the cable paths and connectors. Here, the aim is always, of course, to use cost-efficient twisted-pair cable constructions.
Low-Voltage Differential Signalling (LVDS)
Only the electric driver output and receiver input characteristics are defined with the LVDS signalling standard (TIA/EIA-644-A-2001). This is a purely physical-layer technology, which leaves the definition or usage of upper protocols open and flexible. A LVDS sender includes a constant power source that creates the appropriate digital level change from logic high to logic low at the receiver. It does so by switching current direction (3.5mA nominal) in a pair of lines of the transmission medium. A simple passive termination at the receiver complements the current loop and forms the line termination. Figure 2 summarises the design and the specific benefits of LVDS signalling technology.
Due to the small voltage swing from 250 to 450mV, very high data rates of up to 1Gbit/s and more are possible. Both the static current consumption and the dynamic current portion are very low. In addition, the power driver with its constant impedance can keep power consumption relatively constant over a wide frequency range. Power spikes, common in the switching of TTL or CMOS ("push/pull") outputs, are also minimised through controlled impedance. Finally, termination-resistance power is very low due to the low current (only 1mW).
For signal integrity and EMV behaviour, critical system benefits result from the low signalling level and the differentiated transmission design. Though the electromagnetic fields of the respective conductors of a pair have the same value, they change 180° in phase. The field intensities are proportionally coupled to the distance of the conductors. To achieve optimal cancellation of the fields, this distance should be kept as small as possible in the same way as it’s ensured, for example, in twisted pair cable connections. Just by minimising conductor distances, field intensity portions can, for instance, be reduced to 15dB. The wide ±1V common-mode range of the receiver manages common-mode interference signals. The relatively moderate edge steepness of the signal transition’s dV/dt, in the range of less than 1V/ns, is also favourable with respect to EMV emissions.
